The present disclosure relates to semiconductor devices, and particularly to semiconductor structures including expanded source and drain that extend in an opposite direction of a gate electrode and methods of fabricating the same.
As semiconductor devices are scaled down to smaller dimensions, the deleterious effects of parasitic capacitances on the performance of the semiconductor devices become greater. In particular, the parasitic capacitance between a gate electrode and various contact vias to the source region and the drain region of a field effect transistor becomes a significant portion of the total capacitance of the field effect transistor. Thus, devices are desired that minimize the parasitic capacitance due to proximity of the contact vias to the gate electrode of a field effect transistor.